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<|repo_name|>davidmckain/verilog-ethernet<|file_sep|>/Makefile SOURCES = $(wildcard *.v) $(wildcard components/*.v) $(wildcard components/*/*.v) CFLAGS = --std=ghdl-08 --ieee=synopsys default: ghdl -a $(CFLAGS) $(SOURCES) ghdl -e $(CFLAGS) top ghdl -r $(CFLAGS) top --vcd=top.vcd clean: rm -f *.o *.cf *.cfu <|repo_name|>davidmckain/verilog-ethernet<|file_sep|>/components/ethernet/tx_buffer.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity tx_buffer is generic ( DATA_WIDTH : natural := default_data_width; SIZE : natural := default_tx_buffer_size); port ( clk : in std_logic; din : in std_logic_vector(data_width -1 downto 0); wrn : in std_logic; rdn : in std_logic; full : out std_logic; empty : out std_logic; dout : out std_logic_vector(data_width -1 downto0)); end entity tx_buffer; architecture behavioral of tx_buffer is signal buffer : array(0 to size -1) of std_logic_vector(data_width -1 downto0); signal head : unsigned(size'range); signal tail : unsigned(size'range); signal wrn_dly : std_logic; begin process(clk) begin if rising_edge(clk) then wrn_dly <= wrn; if wrn = '1' and wrn_dly = '0' then buffer(to_integer(head)) <= din; head <= head +1; end if; if rdn = '1' then tail <= tail +1; end if; full <= '0'; empty <= '0'; if head = tail then empty <= '1'; end if; if head = tail +1 then full <= '1'; end if; dout <= buffer(to_integer(tail)); end if; end process; end architecture behavioral;<|repo_name|>davidmckain/verilog-ethernet<|file_sep|>/components/ethernet/mac.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mac is generic ( data_width : natural := default_data_width; preamble_size : natural := default_preamble_size); port ( clk : in std_logic; din : in std_logic_vector(data_width -1 downto0); din_valid : in std_logic; din_ready : out std_logic; mii_rx_clk : in std_logic; mii_rx_dv : in std_logic; mii_rx_er : in std_logic; mii_rx_data : in std_logic_vector(3 downto0); mii_tx_clk : out std_logic; mii_tx_en : out std_logic; mii_tx_er : out std_logic; mii_tx_data : out std_logic_vector(3 downto0)); end entity mac; architecture behavioral of mac is constant start_of_frame : std_logic_vector(7 downto0) := x"55"; constant end_of_frame : std_logic_vector(7 downto0) := x"D5"; begin end architecture behavioral;<|file_sep|># Verilog Ethernet This project contains Verilog implementations of Ethernet components that I have used as learning exercises. The design currently supports only non-GMII PHY interfaces (e.g., MII). It uses Octet-aligned frames. ## License This software is licensed under the MIT License. ## Acknowledgements * https://github.com/larsbrinkhoff/micronaut/ * https://github.com/jdillon/verilog-ethernet<|repo_name|>davidmckain/verilog-ethernet<|file_sep|>/components/mii/mii_to_rgmii.vhd library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mii_to_rgmii is port ( mii_refclk : in std_logic; mii_crs : in std_logic; mii_col : in std_logic; mii_rx_clk : in std_logic; mii_rx_dv : in std_logic; mii_rx_er : in std_logic; mii_rx_data : in std_logic_vector(3 downto0); mii_tx_clk : out std_logic; mii_tx_en : out std_logic; mii_tx_er : out std_logic; mii_tx_data : out std_logic_vector(3 downto0); txd_p : out std_logic_vector(1 downto0); rxd_p : in std_logic_vector(1 downto0); reset_n : in std_ulogic ); end entity; architecture rtl of mii_to_rgmii is signal crs_delayed signal col_delayed signal rx_clk_div signal rx_div_clk signal rx_div_rst signal rx_div_reset signal rx_div_en signal rx_div_count signal tx_clk_div signal tx_div_clk signal tx_div_rst signal tx_div_reset signal tx_div_en signal tx_div_count signal rx_aligned signal tx_aligned signal rx_clk_out signal tx_clk_out signal clk_ok_out signal reset_n_int signal txc_state signal txc_next_state signal txc_init signal txc_endofpacket signal txc_tick signal txc_idle signal txc